As Ultra Large Scale Integration (ULSI) circuit density increases and device feature sizes approach 0.18 microns or less, increased numbers of patterned metal levels are required with decreasing spacing between metal lines at each level to effectively interconnect discrete semiconductor devices on the semiconductor chips. Typically, the different levels of metal interconnections are separated by layers of insulator material. These interposed insulating layers have etched holes filled with a conductive material, referred to as vias, which are used to connect one level of metal to the next. Typically, the insulating layer is silicon oxide (SiO2) having a dielectric constant k (relative to vacuum) of about 4.0 to 4.5.
However, as semiconductor device dimensions decrease and the packing density increases, it is necessary to reduce the spacing between the metal lines at each level of interconnection to effectively wire up the integrated circuits. Unfortunately, as the spacing decreases, the intralevel and interlevel capacitances increase between metal lines, because the capacitance C is inversely proportional to the spacing d between the lines. Therefore, it is desirable to minimize the dielectric constant k of the insulating material (dielectric) between the conducting lines, in order to reduce the RC time constant and thereby increase the performance of the circuit, e.g., the frequency response, since the signal propagation time in the circuit is adversely affected by the RC delay time.
To achieve an insulating layer with a dielectric constant of 3 or less, relatively porous spin-on insulating films are commonly used, such as hydrogen silsesquioxane (HSQ), a silicon polymer with a k of 2.7-3.0, and SiLK™, which is a trademark of the Dow Chemical Company, having a k of 2.65. However, these low-k insulators (low compared to silicon oxide) are usually mechanically weak and some are porous and therefore, do not provide good structural support for integration. Further, absorbed moisture and other chemicals in the porous insulator can cause corrosion of the metal lines. Low-k materials, such as, Black Diamond™, a trademark of Applied Materials, Coral™, a trademark of Novellus, SiCOH and other similar materials are used in the semiconductor industry but are deposited by CVD, which distinguishes them from the spin-on dielectrics.
Copper is the preferred metal that is used on chip multilevel interconnections (both wiring and plugs) to replace aluminum, which has a higher bulk electrical resistivity and a low resistance to electromigration. Copper can be deposited by either electrolytic or electroless deposition and also by Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD), as examples.
However, copper has relatively poor resistance to corrosion. Unlike other metal oxidation (such as aluminum oxidation), copper is readily oxidized to form Cu2O and CuO at relatively low temperatures, e.g., below 200 degrees C, and no self-protective oxide layer forms to prevent the copper from further oxidation. Oxidized copper degrades the electrical and mechanical properties of the copper interconnect. Accordingly, a protection, or encapsulation, e.g., diffusion barrier, layer of high corrosion resistance material is necessary to cover exposed copper surfaces.
A variety of materials are known for forming diffusion barriers on copper. Such materials include Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN and TaSiN, as examples, which can be deposited by CVD or PVD. More recently, electrolessly deposited CoWP has been used as a barrier material to encapsulate a conductor material. Furthermore, the W in the CoWP significantly enhances the barrier properties.
However, in very narrow spaces like those found between first level metal lines in 0.18 or less micron technologies, if the copper diffusion barrier cap layer is selectively deposited onto the exposed copper of the previously planarized surface there is some lateral (sideways) growth which is proportional to the thickness of the selectively deposited layer. When the lateral growth exceeds half the distance between copper lines, the cap layer can make contact with the adjacent cap layer to create an electrical short. Therefore, in some technologies a very thin layer of CoWP, proposed to achieve an improvement in electromigration, would be less prone to form electrical shorts. But an extremely thin layer is insufficient as a copper diffusion barrier and therefore, an additional cap layer of, for example, SiN (Si3N4), SiC, SiCN or BlokTM (a barrier low-k insulator material developed by Applied Materials, Inc.) is required.